1. Field of the Invention
The present invention relates to a semiconductor device in which humps are suppressed.
2. Description of the Related Art
In recent years, in order to respond to demand for shrinking chip size, still higher integration of a transistor is required. One solution to this problem is an element isolation technology called shallow trench isolation (STI). However, when STI is adopted, a gate oxide film becomes thinner at an interface between a diffusion layer port ion and an STI port ion than at other port ions, and thus, a parasitic transistor is formed.
FIG. 4 is a graph illustrating a relationship between gate voltage and drain current in a transistor having a parasitic transistor formed therein. In FIG. 4, a curve A illustrates a relationship between gate voltage and drain current in a main transistor while a curve B illustrates a relationship between gate voltage and drain current in a parasitic transistor. Equivalently, a transistor having a parasitic transistor formed therein can be regarded as two transistors having different threshold voltages connected in parallel. Therefore, the relationship between gate voltage and drain current in a transistor having a parasitic transistor formed therein is as illustrated by a curve C which is a combination of the curves A and B. As illustrated by the curve C, when a parasitic transistor is formed, hump characteristics appear.
Japanese Patent Application Laid-open No. 2000-101084 discloses a conventional technology to suppress the hump characteristics. A field effect transistor described in Japanese Patent Application Laid-open No. 2000-101084 includes source and drain regions, a channel region between the source and drain regions, isolation regions in a substrate, and a gate including a gate dopant on the channel region. The gate includes a region in which the gate dopant is substantially depleted at least in a region in which the gate overlaps the channel region and the isolation region. It is thought that, because a threshold voltage in a channel corner region beneath the depletion region increases compared with that in the channel region between corner regions, the hump characteristics are improved.
Japanese Patent Application Laid-open No. 2004-303911 discloses a conventional technology which relates to a gate electrode, though this technology does not relate to improvement of the hump characteristics. A gate electrode of a metal insulated semiconductor FET (MISFET) described in Japanese Patent Application Laid-open No. 2004-303911 has an n+ region and a p+ region. Further, the two regions are connected by metal wiring in ohmic contact, which makes voltage at the n+ region always equal to voltage at the p+ region. Further, an element region of the MISFET including an n+ source region and an n+ drain region is isolated from other MISFETs by an insulating film for element isolation. A MISFET having such a structure has, in an off state, a small leakage current because of a high threshold and has, in an on state, a large ON current because of a low threshold.
However, in the technology disclosed in Japanese Patent Application Laid-open No. 2000-101084, an impurity diffuses in the depletion region from a region adjacent to the region. Therefore, concentration of the impurity in the depletion region varies widely, and, as a result, the characteristics of the semiconductor device varies widely.